Backwards Tantalums

We all are aware that the tantalum capacitor is a polar device and must be oriented properly to be functional.  However the question does arise from time to time concerning tantalum capacitors that are mistakenly assembled backwards.  There also can be questions about reliability if there is reverse voltage applied to the capacitor for a short period of time.  These questions do not have a straightforward and clear answer.
The tantalum capacitor begins by sintering a porous tantalum powder to form the anode of the capacitor.  The dielectric layer, Ta2O5 is then grown using an electrochemical process and the thickness depends on the electrolyte chemistry and the forming voltage.  A higher forming voltage results in a thicker dielectric and a high rated voltage part.  The cathode has typically consisted of MnO2 although lately polymers are also used. For more detailed constructional details, consult reference 1 or similar articles.
If a tantalum capacitor is reversed biased there is an increased leakage current and the voltage/current curve resembles a diode curve.  There are various physical theories to account for this asymmetrical behavior.  John Prymak, Kemet, explains this as a reduction of the Ta2O5 resulting in Ta nodes extending into the dielectric layer (ref 2). Alexander Teverovsky, NASA, details asymmetric metal-insulator semiconductor structure to explain the experimental data (ref 4).  There are other theories as well. Whatever the correct theory, what does the experimental data say about reverse biased tantalum capacitors?  The electrical characteristics depend on the magnitude of the reverse bias voltage.  If the reverse voltage is small, then there is almost no leakage in leakage current and erratic changes in current are not seen. How small is small?  It has been measured (ref 4) than reverse voltages as low as 6% of the rated voltage can result in erratic changes in leakage current.  There is a two stage degradation process and this erratic change in leakage current is a precursor to an actual hard failure.  During the first state where there the leakage current increases, there is a period of stability which could extend for 100s of hours.   Interestingly, the effects of the reverse current at this state are reversible.  That is, applying a forward voltage (or even letting it sit unbiased) will reverse the degradation process if it hasn't progressed too far.  If the reverse bias is applied to long periods of time, the stage 2 degradation process occurs and the part is permanently damaged.  Studies have shown that there are variations is reverse bias characteristics across different parts and lots of parts.  Some lots could survive reverse bias voltages of 15% for many hours before entering into stage 2 failure.
So if a tantalum capacitor is installed backwards in an assembly, could it make it through the test process and get to the end customer?  The answer is yes, it is possible. Let’s say the circuit design uses a 50% derating so the reverse bias voltage would be is 50% of the rated voltage or below.  See reference 3 where studies were performed at both 50% and 25% reverse bias voltage. At 50% reverse voltage, most of the capacitors failed within 15 minutes of the test.  At only 25% reverse voltage most of the capacitors failed within 250 hours.  So then, depending on the percentage of reverse bias voltage and the length of the test process, a tantalum capacitor may or may not failure during product testing.
References
1. J. Gill, Basic Tantalum Capacitor Technology, AVX Technical Brochure
2. J. Prymak, A Theory of Reverse Voltage Failures in SMT Tantalum/Electrolytic Capacitors, 2002 CARTS
3. A. Teverovsky, Reverse Bias Behavior of Surface Mount Solid Tantalum Capacitors, CARTS 2002
4. A. Teverovsky, Effect of Reverse Bias Stress on Leakage Currents and Breakdown Voltages of Solid Tantalum Capacitors, 2011 CARTS

Hot Melt Conformal Coating?

The Ohio Chapter of the SMTA met on September 18th the meeting was conformal coatings: surface preparation, material selection, application and rework. Jim Stockhausen of Elantas PDG, Inc. presented on material selection. Jim briefly mentioned a class of materials that could be called “hot-melt” conformal coating. These are materials that could be applied either with a dispensing machine or with a hot melt gun. The reason I was interested in this material is that there are times that a spot coating is needed over a specific component or area of the assembly. Dispensing material with a hot melt gun over a specific component could be a better solution than either brushing on a traditional coating or sending the assembly through an in-line conformal coating process.

The hot melt conformal coatings are different that the common hot melt adhesives. One such material is Bectron MR 3406. This coating material is based on polyolefin chemistry in contrast to the conventional polyamide based materials used for adhesives. This results in the coating having better adhesion and absorbing less moisture compared to the adhesive material. The MR3406 is rated to 130C and has low humidity absorption. It is resistant to acids, solvents and fungus growth. It generally meets the IPC-CC-830 tests although it is not rated to this specification because there is no category defined for this material. Rework is easy because it can be softened and peeled away.

I do have a couple of concerns. First, since the material softens at 150C, the temperature at the nozzle must by about 190C-200C. Although the coating cools quickly, is there a danger of thermal shock damage to the component or PCB? Also the adhesion to PCB surfaces with flux residues would need to be tested. I don’t know of any immediate application for this material but it could potentially be used in spot coating applications.

PCB Laminate Suppliers not Meeting the RoHS Challenge

The implementation of RoHS compliant materials and RoHS compatible soldering processes has driven the PCB laminate suppliers to provide laminates that are very robust to thermal processes. Common qualification tests include 6X reflows at 260C and time to delaminate at 260C and 288C. A common criterion in IPC-4101 is 30 minutes at 260C with no delamination. An unforeseen effect of increasing the thermal robustness is that the PCB laminates have become more brittle. A major contributing cause is the use of phenolic cured PCB materials compared to the pre-RoHS dicy cured materials. This brittleness results in an increasing incidence of pad cratering and component breakage from the PCB pads. Pad cratering occurs when PCBs assemblies with BGAs are flexed. This could occur at in-circuit test or during process such as depanelization. Although this problem has been observed in the industry before 2005 (1), the PCB laminate suppliers have still not addressed this issue by improving the mechanical robustness of laminates. It does appear that the laminate suppliers are dragging their feet on this issue. Currently the RoHS compatible laminates are over designed for thermal robustness and under designed for mechanical strength. One would think that after 8 years the laminate suppliers would now offer new material solutions to this problem.

It would be desirable to define an industry standard test that the suppliers could use to provide laminate strength data to customers. There are some industry standard test methods such as the ball pull test (IPC-9708) and the spherical bend test (IPC-9707). There is no test acceptance criterion within these procedures and the laminate industry does not publish data from these tests on data sheets or test reports.

References
1. F. Joyce, Transient Bend Board Flexure Initiative, IPC Presentation, June 2005
2. M. Ahmad, Comprehensive Methodology to Characterize and Mitigate BGA Pad Cratering in Printed Circuit Boards, SMTA Journal, Vol 22 Issue 1, 2009
3. C. Tulkoff, SMTA Pad Cratering Webinar, April 10, 2012

Ceramic Capacitor Reliability Revisited

In the last decade, the volumetric efficiency (capacitance/volume) of ceramic capacitors has been rapidly increasing. To achieve this the dielectric layer thickness has been decreasing to below 1 micron which results in a higher electric field strength across the electrode layers. What effect does this have on reliability? In years past it was expected that if MLCCs are used within the specified temperature and voltage limits that wear-out will not be a concern. Clive Hendricks, Intel Corporation, created considerable interest within the industry with his paper at the 2010 CARTS. In his paper he concluded that the industry standard life testing was not adequate in predicting the reliability of MLCCs. Accelerated life tests were performed on 0402, 2,2uF, X6S, 4V capacitors. Using the familiar (at least in the capacitor community) Prokopowicz-Vaskas equation for MLCC life acceleration with voltage and temperature, Clive Hendricks reported considerable variation with different suppliers. The predicted useful lifetime varied from 509 years to only 8 years. Is this an indication that we should pay more attention to MLCC wear-out concerns?

Two recent published papers have now weighed in on this issue. N. Kubodera, et al, from Murata Manufacturing Co., have published a study in the 2012 CARTS. This study reviewed the MLCC wear-out mechanism It was found that the standard temperature acceleration models were accurate. However this testing showed that the voltage acceleration equation showed two different acceleration factors. At higher electric field strengths the acceleration factor was greater than for lower field strengths. This means that tests at higher voltages may be overly pessimistic concerning predicted field life. Murata then developed a voltage acceleration model that covered a wide range of electric field strengths. The result of this model is a log-normal distribution. One aspect that needs further work is a combined temperature/voltage model that is useful at higher voltage stresses.

David Liu, MEI Technologies, NASA Goddard Space Flight Center, also has been doing extensive research in this area. His study found two separate failure distributions. The earlier failures in this study showed a different failure distribution slope compared to the later failures. It was determined the early failures were due to avalanche-like leakage current breakdown due to defects in the ceramic. It was concluded that the later failures were due to intrinsic causes – the diffusion of oxygen vacancies under an electric field. The early failures due to defects in the ceramic is entirely logical since due to the decreasing dielectric thickness. One positive aspect to the base metal electrode (BME) capacitors, which are now 90% of the capacitors used today, is that the grain sizes are are smaller than the precious metal electrode capacitors.

The story on MLCC wear-out is not yet finished. As the dielectric layer thickness of high capacity MLCCs continues to decrease, the reliability must be assessed. The reliability of decoupling capacitors must be very high since there are many capacitors used per design. MLCC reliability is an area that needs to be closely watched as capacitive efficiency increases.

References:

1. C. Hendricks, et al, Reliability Challenges for CPU Decoupling MLCC, 2010 CARTS

2. N. Kubodera, et al, Study of the Long Term Reliability for MLCCs, 2012 CARTS

3. D. Liu and M. Sampson, Some Aspects of the Failure Mechanisms in BaTiO3-Based Multilayer Ceramic Capacitors, 2012 CARTS

Thickness Critical to Immersion Tin Success

As with all PCB surface finish choices, immersion tin has both positive and negative aspects. It is a flat surface that is widely available and has performed well in mixed flowing gas corrosion testing.  For these reasons this coating is an alternative to HASL coating for fine pitch circuit features.  There are some negative features that must also be considered including shelf life.  An immersion tin PCB plating uses a thin tin plating directly over the PCB copper pad.  The tin protects the copper pad from oxidation and therefore the pad remains solderable for component assembly soldering. Common industry standards specify the thickness of the tin plating has a minimum thickness of only 1.0 micron. This may have been fine for Sn/Pb soldering however a 1.0 micron coating proves marginal for an extended shelf life and a Pb-free double reflow process. The reason for this is that with time and temperature the tin and underlying copper will alloy together and form a tin-copper intermetallic compound (IMC) and in this way the pure tin plating is reduced.  This pure tin plating on top of the copper and IMC is critical to good solderability.  Studies have shown that there must be at least 0.2 to 0.3 micron of pure tin going into the second pass of a double reflow process to be successful. Therefore the initial tin plating must be thick enough so that even if some (or most) of the tin plating is alloyed in to an IMC layer there is a minimum amount of pure tin plating remaining.  The depletion of tin and the growth of the IMC occurs naturally as the PCBs sit on the shelf as well as during any soldering processes.  

For these reasons, controlling the shelf life of immersion tin PCBs is important.  Generally speaking PCB suppliers state that the shelf life of immersion tin PCBs is six months which is a short time within a high mix electronic assembly facility. Can a slightly thicker tin coating improve the situation? In a study I performed in 2009 I showed that the shelf life is highly sensitive to the plating thickness.  An increased thickness of only 1.1 microns extends the shelf life to 1 year and a plating thickness of 1.2 microns extends the shelf life to 2 years.  This being the case, one may ask why not increase the specification to 1.2 microns?  This idea has been met with resistance from the PCB suppliers since the time in the plating bath would need to be extended to achieve this. The immersion tin plating process is a substitution plating process where the tin is plated on the surface and copper is driven into the plating solution according to the chemical equation Sn2+ + Cu -> Cu2+ + Sn.  As the tin plating builds up it begins to prevent the copper from transferring into solution and therefore the plating process is self-limiting.  However it is possible to achieve a 1.2 micron plating thickness by increased time the plating bath.  Atotech, a major immersion tin supplier, actually recommends 1.2 microns of tin for success in a Pb-free double reflow process.  However the suppliers are unwilling to agree to an increased specification for fear of process variability and lot rejections. For these reasons careful attention must be given to control the shelf life of immersion tin PCBs.  

References

1.  Investigation of the Recommended Immersion Tin Thickness for Lead Free Soldering, Atotech Technical Information, January 2005

New Light on a BGA Soldering Problem

BGA/CSP/WSP array solder joint failures can be very vexing for several reasons.  First, BGA solder joint opens are difficult to diagnose in the assembly because BGA electrical problems are always difficult to diagnose due to the lack of access to electrical test points and the high complexity of the circuitry.  The second troublesome aspect is that reworking a BGA is difficult and third, there is the possibility of the assembly passing functional test and having latent field failures.  Therefore very high solder joint assembly yields are required. High solder joint yields were the original promise when BGA packages were introduced many years ago but based on the numerous publications of head-in-pillow failures there is widespread inconsistency on achieving those high yields (see my 2010 blog posting on BGAs). Now there is another failure mechanism which is causing problems - non-wet opens.

Non-wet opens (NWO) are a problem in BGA/CSP soldering where the solder paste does not wet the PCB pad.  These failures can be misdiagnosed as 1) head-in-pillow failures, 2) failures due to a clogged stencil or 3) a PCB solderability problem.  Possibly because of  misdiagnoses there has not been any published research into the various factors that result in this failure.  That is until the recent SMTA International conference in October.  The team at Intel presented an excellent paper [1] that is a valuable resource in learning about this problem.  Here are some of the important findings of this research.
1.   One of the key findings is that solder paste has a considerable influence on NWO open failures.  Both the wetting activity and the paste tackiness are important.  Intel was able to turn NWO on and off just by switching the solder paste.  
2.   Paste volume also was shown to add some margin to prevent NWOs.  This factor is not as large as the paste formulation.
3.   The soak profile during reflow is a factor.  Longer soak times produce fewer NWOs.
4.   Inert atmosphere soldering did not have a significant influence.
5.   PCB surface finish showed some effect.  Interestingly, lead-free HASL and OSP were the poorest finishes compared with immersion silver.
6.   Component warpage is also a factor in a more complicated way.  Concave or convex warpage can change the failure mode from NWO to HiP.

In summary, this paper is important since it is the first paper to shed more light on the nature of NWOs.  The influence of paste formulation is especially significant.   This paper should prompt further investigation especially by the solder paste suppliers.  In fact, several solder paste suppliers are actively and quietly researching how to mitigate this risk.  It is possible that the development of head-in-pillow resistant solder paste has resulted in the side effect of more NWOs. These types of unintended side effects are very common as technology advances. Due to the high solder joint yields required of today’s complex electronic assemblies, it is urgent that progress be made to eliminate this problem.

References
1.  D. Amir, et al.  The Challenges of Non Wet Open BGA Solder Defect, SMTAI, October 2012